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isplsi 5128ve in-system programmable 3.3v superwide? high density pld 1 5128ve_05 copyright ? 2002 lattice semiconductor corp. all brand or product names are trademarks or registered trademarks of their respec tive holders. the specifications and information herein are subject to change without notice. lattice semiconductor corp., 5555 northeast moore ct., hillsboro, oregon 97124, u.s.a. january 2002 t el. (503) 268-8000; 1-800-lattice; fax (503) 268-8556; http://www.latticesemi.com features ? second generation superwide high density in-system programmable logic device ? 3.3v power supply ? user selectable 3.3v/2.5v i/o ? 6000 pld gates / 128 macrocells ? 96 i/o pins available ? 128 registers ? high-speed global interconnect ? superwide generic logic block (32 macrocells) for optimum performance ? superwide input gating (68 inputs) for fast counters, state machines, address decoders, etc. ? interfaces with standard 5v ttl devices ? high performance e 2 cmos ? technology ? f max = 180 mhz maximum operating frequency ? t pd = 5.0 ns propagation delay ? ttl/3.3v/2.5v compatible input thresholds and output levels ? electrically erasable and reprogrammable ? non-volatile ? programmable speed/power logic path optimization ? in-system programmable ? increased manufacturing yields, reduced time-to- market, and improved product quality ? reprogram soldered devices for faster debugging ? 100% ieee 1149.1 boundary scan testable and 3.3v in-system programmable ? architecture features ? enhanced pin-locking architecture with single- level global routing pool and superwide glbs ? wrap around product term sharing array supports up to 35 product terms per macrocell ? macrocells support concurrent combinatorial and registered functions ? macrocell registers feature multiple control options including set, reset and clock enable ? four dedicated clock input pins plus macrocell product term clocks ? programmable i/o supports programmable bus hold, pull-up, open drain and slew rate options ? four global product term output enables, two global oe pins and one product term oe per macrocell global routing pool (grp) boundary scan interface input bus input bus generic logic block generic logic block input bus generic logic block input bus generic logic block isplsi 5000ve description the isplsi 5000ve family of in-system programmable high density logic devices is based on generic logic blocks (glbs) of 32 registered macrocells and a single global routing pool (grp) structure interconnecting the glbs. outputs from the glbs drive the global routing pool (grp) between the glbs. switching resources are pro- vided to allow signals in the global routing pool to drive any or all the glbs in the device. this mechanism allows fast, efficient connections across the entire device. each glb contains 32 macrocells and a fully populated, programmable and-array with 160 logic product terms and three extra control product terms. the glb has 68 inputs from the global routing pool which are available in both true and complement form for every product term. the 160 product terms are grouped in 32 sets of five and sent into a product term sharing array (ptsa) which allows sharing up to a maximum of 35 product terms for a single function. alternatively, the ptsa can be by- passed for functions of five product terms or less. the three extra product terms are used for shared controls: reset, clock, clock enable and output enable. functional block diagram
specifications isplsi 5128ve 2 functional block diagram figure 1. isplsi 5128ve functional block diagram (96-i/o) package type multplexed signals 128 tqfp i/o 59 / clk2 i/o 65 / clk3 i/o 0 / toe global routing pool (grp) boundary scan interface input bus input bus generic logic block generic logic block input bus generic logic block input bus generic logic block 1 toe vccio i/o 1 i/o 2 i/o 3 i/o 20 i/o 21 i/o 22 i/o 23 i/o 24 i/o 25 i/o 26 i/o 27 i/o 44 i/o 45 i/o 46 i/o 47 clk0 clk1 1 clk2 1 clk3 i/o 51 i/o 50 i/o 49 i/o 48 i/o 71 tdi tdo i/o 70 i/o 69 i/o 68 i/o 75 i/o 74 i/o 73 i/o 72 tck tms i/o 95 goe1 goe0 i/o 94 i/o 93 i/o 92 1. clk2, clk3 and toe signals are shared with i/o signals. use the table below to determine which i/o is shared. reset
specifications isplsi 5128ve 3 isplsi 5000ve description (continued) the 32 registered macrocells in the glb are driven by the 32 outputs from the ptsa or the ptsa bypass. each macrocell contains a programmable xor gate, a pro- grammable register/latch and the necessary clocks and control logic to allow combinatorial or registered opera- tion. the macrocells each have two outputs, combinatorial and registered. this dual output capability from the macrocell allows efficient use of the hardware resources. one output can be a registered function for example, while the other output can be an unrelated combinatorial function. a direct register input from the i/o pad facili- tates efficient use of this feature to construct high-speed input registers. macrocell registers can be clocked from one of several global or product term clocks available on the device. a global and product term clock enable is also available to each register, eliminating the need to gate the clock to the macrocell registers. reset for the macrocell register is provided from the global signal, its polarity is user- selectable. the macrocell register can be programmed to operate as a d-type register or a d-type latch. the 32 outputs from the glb can drive both the global routing pool and the device i/o cells. the global routing pool contains one input from each macrocell output and one input from each i/o pin. the input buffer threshold has programmable ttl/3.3v/ 2.5v compatible levels. the output driver can source 4ma and sink 8ma in 3.3v mode. the output drivers have a separate vccio reference input which is inde- pendent of the main vcc supply for the device. this feature allows individual output drivers to drive either 3.3v (from the device vcc) or 2.5v (from the vccio pin) output levels while the device logic and the output current drive are powered from device supply (vcc). the output drivers also provide individually programmable edge rates and open drain capability. a programmable pullup resistor is provided to tie off unused inputs. additionally, a programmable bus-hold latch is available to hold tristate outputs in their last valid state until the bus is driven again by some device. the isplsi 5000ve family features 3.3v, non-volatile in- system programmability for both the logic and the interconnect structures, providing the means to develop truly reconfigurable systems. programming is achieved through the industry standard ieee 1149.1-compliant boundary scan interface. boundary scan test is also supported through the same interface. an enhanced, multiple cell security scheme is provided that prevents reading of the jedec programming file when secured. after the device has been secured using this mechanism, the only way to clear the security is to execute a bulk-erase instruction. isplsi 5000ve family members the isplsi 5000ve family ranges from 128 macrocells to 512 macrocells and operates from a 3.3v power supply. all family members will be available with multiple package options. the isplsi 5000ve family device matrix showing the various bondout options is shown in the table below. the interconnect structure (grp) is very similar to lattice's existing isplsi 1000, 2000 and 3000 families, but with an enhanced interconnect structure for optimal pin locking and logic routing. this eliminates the need for registered i/o cells or an output routing pool. the isplsi 5000ve encompasses the innovative fea- tures of the isplsi 5000va family with several enhancements. the macrocell is optimized and the t- type flip flop option is removed. to improve the efficiency of design fits, the product term reset logic is simplified and the polarity option as well as the global preset function are removed. the programmable output-delay feature (skew option) is also removed. as a result, the isplsi 5000ve is not jedec compatible with the isplsi 5000va. isplsi 5000va and 5000ve pinouts may differ in the same package, however all programming and power/ground pins are located in the same locations. table 1. isplsi 5000ve family package type isplsi 5128ve device glbs macrocells 128 tqfp 256 fpbga 272 bga 388 fpbga 388 bga 4 128 96 i/o ? ? ? ? 8256 96 i/o 144 i/o 144 i/o ? ? 12 384 ? 192 i/o 192 i/o ? ? 16 512 ? 100 tqfp ? 72 i/o ? ?192 i/o 192 i/o 256 i/o 256 i/o isplsi 5256ve isplsi 5384ve isplsi 5512ve
specifications isplsi 5128ve 4 figure 2. isplsi 5128ve block diagram (96 i/o) 32 24 i/o 32 32 160 160 pt 160 32 d q 32 24 i/o 68 dq 160 160 68 160 pt 32 32 24 i/o 160 160 pt 160 32 d q 32 24 i/o 68 dq 160 160 68 160 pt 32 32 32 224 24 24 24 24 24 24 24 24 3 3 pt 3 pt 3 3 3 pt 3 pt 3 reset goe1 goe0 clk1 clk0 io0/toe clk3 clk2 glb0 glb3 glb1 glb2
specifications isplsi 5128ve 5 figure 3. isplsi 5000ve generic logic block (glb) 0 12 66 67 macrocell 0 pt 160 macrocell 1 macrocell 15 macrocell 31 pt 9 pt 8 pt 7 pt 6 pt 5 pt 0 pt 1 pt 2 pt 3 pt 4 pt 79 pt 78 pt 77 pt 76 pt 75 pt 159 pt 158 pt 157 pt 156 pt 155 shared pt clock global ptoe 0 ... 3 4 shared pt clock global ptoe 0 ... 3 4 shared pt clock global ptoe 0 ... 3 4 to i/o pad shared pt clock global ptoe 0 ... 3 4 from grp ptsa global ptoe bus from ptsa from ptsa from ptsa from ptsa pt 161 pt 162 shared pt reset shared pt reset shared pt reset shared pt reset ptsa bypass pt clock pt preset pt reset ptoe ptsa bypass pt clock pt preset pt reset ptoe ptsa bypass pt clock pt preset pt reset ptoe ptsa bypass pt clock pt preset pt reset ptoe to grp to i/o pad to grp to i/o pad to grp to i/o pad to grp
specifications isplsi 5128ve 6 figure 4. isplsi 5000ve macrocell ptsa dq r p ptsa bypass pt clock pt reset clk en r/l ptoe shared pt clock goe0 goe1 pt preset speed/ power toe clk0 clk1 clk clk2 clk3 global reset shared pt reset global ptoe 2 global ptoe 3 global ptoe 0 global ptoe 1 vccio vccio vcc slew rate open drain 2.5v/3.3v output i/o pad to grp to grp input threshold 2.5v/3.3v note: not all macrocells have i/o pads.
specifications isplsi 5128ve 7 global clock distribution the isplsi 5000ve family has four dedicated clock input pins: clk0 - clk3. clk0 input is used as the dedicated master clock that has the lowest internal clock skew with no clock inversion to maintain the fastest internal clock speed. the clock inversion is available on the remaining clk1 - clk3 signals. by sharing the pins with the i/o pins, clk2 and clk3 can not only be inverted but are also available for logic implementation through grp signal routing. figure 5 shows these different clock distribution options. figure 5. isplsi 5000ve global clock structure clk0 clk1 clk 0 (dedicated pin) clk 1 (dedicated pin) io/clk 2 (shared pin) io/clk 3 (shared pin) clk2 clk3 to/from grp global reset reset (dedicated pin) to/from grp io0/toe (shared pin) toe to/from grp
specifications isplsi 5128ve 8 figure 6. boundary scan register circuit for i/o pins figure 7. boundary scan register circuit for input-only pins normal function oe extest update dr scanout (to next cell) clock dr scanin (from previous cell) shift dr normal function toe dq dq dq d 1 0 1 0 1 0 q dq i/o pin reset bscan registers bscan latches highz 0 prog_mode extest 1 0 1 scanout (to next cell) clock dr scanin (from previous cell) shift dr dq input pin 0 1
specifications isplsi 5128ve 9 figure 8. boundary scan waveforms and timing specifications tms tdi tck tdo data to be captured data to be driven out valid data valid data valid data valid data data captured btsu t bth t btcl t btch t btcp t btvo t btco t btoz t btcpsu t btcph t btuov t btuco t btuoz t symbol p arameter min max units t btcp tck [bscan test] clock pulse width 125 ? ns t btch tck [bscan test] pulse width high 62.5 ? ns t btcl tck [bscan test] pulse width low 62.5 ? ns t btsu tck [bscan test] setup time 25 ? ns t bth tck [bscan test] hold time 25 ? ns t rf tck [bscan test] rise and fall time 50 ? mv/ns t btco tap controller falling edge of clock to valid output ?25ns t btoz tap controller falling edge of clock to data output disable ?25ns t btvo tap controller falling edge of clock to data output enable ?25ns t btcpsu bscan test capture register setup time 25 ? ns t btcph bscan test capture register hold time 25 ? ns t btuco bscan test update reg, falling edge of clock to valid output ?50ns t btuoz bscan test update reg, falling edge of clock to output disable ?50ns t btuov bscan test update reg, falling edge of clock to output enable ?50ns
specifications isplsi 5128ve 10 absolute maximum ratings 1, 2 supply voltage v cc .................................. -0.5 to +5.4v input voltage applied ............................... -0.5 to +5.6v tri-stated output voltage applied ........... -0.5 to +5.6v storage temperature ................................ -65 to 150 c case temp. with power applied .............. -55 to 125 c max. junction temp. (t j ) with power applied ... 150 c 1. stresses above those listed under the ?absolute maximum ratings? may cause permanent damage to the device. functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion is not implied (while programming, follow the programming specifications). 2. compliance with the thermal management section of the lattice semiconductor data book or cd-rom is a requirement. dc recommended operating condition symbol table 2-0005/5kve v cc v ccio parameter supply voltage i/o reference voltage commercial t a = 0 c to +70 c min. max. units 3.00 2.3 3.60 3.60 v industrial t a = -40 c to +85 c 3.00 3.60 v v capacitance (t a =25 c,f=1.0 mhz) symbol table 2-0006/5kve c parameter clock capacitance 10 units typical test conditions 2 pf v = 3.3v, v = 0.0v cc ck c i/o capacitance 10 1 pf v = 3.3v, v = 0.0v cc i/o c global input capacitance 10 3 pf v = 3.3v, v = 0.0v cc g erase reprogram specification table 2-0008/5kve parameter minimum maximum units isplsi erase/reprogram cycles 10000 ? cycles
specifications isplsi 5128ve 11 switching test conditions input pulse levels table 2-0003/5kve input rise and fall time input timing reference levels ouput timing reference levels output load gnd to v ccio min 1.5ns 10% to 90% 1.5v 1.5v see figure 9 3-state levels are measured 0.5v from steady-state active level. output load conditions (see figure 9) test condition r1 3.3v 2.5v r2 cl a 35pf d 35pf b 35pf 35pf active high slow slew active low c 5pf 5pf 511 ? 511 ? 511 ? 475 ? 475 ? 475 ? r1 r2 316 ? 316 ? 316 ? 348 ? 348 ? 348 ? active low to z at v +0.5v ol active high to z at v -0.5v oh table 2-0004a/5kve dc electrical characteristics for 3.3v range 1 over recommended operating conditions figure 9. test load v ccio r 1 r 2 c l * device output test point * c l includes test fixture and probe capacitance. 0213d v ol symbol 1. i/o voltage configuration must be set to vcc. table 2-0007/5kve v oh v ih v il parameter output low voltage output high voltage input high voltage input low voltage v ccio = min , i ol = 8 ma v ccio = min , i oh = -4 ma condition min. typ. max. units ? 2.4 2.0 -0.3 ? ? ? ? 0.4 ? 5.25 0.8 v v v ccio i/o reference voltage 3.0 ? 3.6 v v v
specifications isplsi 5128ve 12 dc electrical characteristics over recommended operating conditions dc electrical characteristics for 2.5v range 1 over recommended operating conditions v ih symbol 2.5v/5128ve v oh parameter input high voltage output high voltage v ccio=min , i oh = -2ma v ccio=min , i ol = 2ma condition min. typ. max. units 1.7 1.8 ? ? 5.25 ? v v ccio v il i/o reference voltage input low voltage 2.3 -0.3 ? ? 2.7 0.7 v v v v ccio=min , i oh = -100 a 2.1 ? ? v ??0.6v v ccio=min , i ol = 100 a ??0.2v v ol output low voltage 1. i/o voltage configuration must be set to vccio. symbol 1. pullup is capable of pulling to a minimum voltage of v oh under no-load conditions. dc char_5kve i pu i bhl parameter i bhh i bhlo 1 i/o active pullup current bus hold low sustaining current bus hold high sustaining current bus hold low overdrive current i ih i il input or i/o high leakage current input or i/o low leakage current 0v v v (max.) in il condition min. typ. max. units ? ? ? ? 40 -40 ? ? ? ? ? ? ? ? -10 10 -200 50 ? ? 550 a a a a a a i bhlh i bht bus hold high overdrive current bus hold trip points ? v il ? ? -550 v ih a v i vccio current needed for v ccio pin all i/os pulled-up, (total i/os * i pumax )? ? 30 ma a (v ccio -0.2)v v in v ccio v ccio v in 5.25v 0v v in v il 0v v in v ccio 0v v in v ccio v in = v il(max) v in = v ih(min)
specifications isplsi 5128ve 13 external switching characteristics over recommended operating conditions . m a r a p t s e t 3 . d n o c n o i t p i r c s e d 5 , 4 0 8 1 -5 2 1 - s t i n u . n i m. x a m. n i m. x a m t 1 d p 6 as s a p y b t p 5 , y a l e d . p o r p a t a d?0 . 5?5 . 7s n t 2 d p 6 ay a l e d n o i t a g a p o r p a t a d?0 . 7?5 . 9s n f x a m ak c a b d e e f l a n r e t n i h t i w y c n e u q e r f k c o l c 1 0 8 1? 5 2 1? z h m f ) . t x e ( x a m ?) 1 o c t + 2 u s t ( / 1 , k c a b d e e f . t x e h t i w . q e r f k c o l c 3 3 1?7 8? z h m f ) . g o t ( x a m ?e l g g o t x a m , y c n e u q e r f k c o l c 2 7 2 2? 7 6 1? z h m t 1 u s ?s s a p y b t p 5 , k l c e r o f e b e m i t p u t e s . g e r b l g5 . 3?0 . 5? s n t 1 o c 6 ay a l e d t u p t u o o t k c o l c . g e r b l g?0 . 3?5 . 4s n t 1 h ?s s a p y b t p 5 , k c o l c r e t f a e m i t d l o h . g e r b l g0 . 0?0 . 0? s n t 2 u s ?k c o l c e r o f e b e m i t p u t e s . g e r b l g5 . 4?0 . 7? s n t 2 h ?k c o l c r e t f a e m i t d l o h . g e r b l g0 . 0?0 . 0? s n t 3 u s ?h t a p . g e r t u p n i , k c o l c e r o f e b e m i t p u t e s . g e r b l g5 . 2?5 . 3? s n t 3 h ?h t a p . g e r t u p n i , k c o l c r e t f a e m i t d l o h . g e r b l g5 . 0?5 . 0? s n t 1 r ay a l e d t u p t u o o t n i p t e s e r . t x e?0 . 6? 0 . 0 1s n t 1 w r 7 ?n o i t a r u d e s l u p t e s e r . t x e 5 . 3?0 . 5? s n t s i d / n e t p 6 c / be l b a s i d / e l b a n e t u p t u o m r e t t c u d o r p l a c o l?0 . 6?5 . 8s n t s i d / n e t p g 6 c / be l b a s i d / e l b a n e t u p t u o m r e t t c u d o r p l a b o l g?0 . 7? 0 . 4 1s n t s i d / n e g 6 c / be l b a s i d / e l b a n e t u p t u o o t t u p n i e o l a b o l g?5 . 3?5 . 5s n t s i d / n e t 6 c / be l b a s i d / e l b a n e t u p t u o o t t u p n i e o t s e t?5 . 5? 5 . 0 1s n t h w ?h g i h , n o i t a r u d e s l u p k c o l c . c n y s . t x e 2 . 2?0 . 3? s n t l w ?w o l , n o i t a r u d e s l u p k c o l c . c n y s . t x e 2 . 2?0 . 3? s n . k c a b d e e f p r g g n i s u r e t n u o c t i b - 6 1 d r a d n a t s . 1 s p e . 1 e v 8 2 1 5 . t x e g n i m i t . % 0 5 n a h t r e h t o f o e l c y c y t u d k c o l c a r o f w o l l a o t s i s i h t . ) l w t + h w t ( / 1 n a h t s s e l e b y a m ) e l g g o t ( x a m f . 2 0 . 2 . v g n i m i t . n o i t c e s s n o i t i d n o c t s e t g n i h c t i w s e c n e r e f e r . 3 - h g i h d n a , 0 k l c , b l g 1 f o d a o l p r g a , t u o n a f a s t p e s a c t s r o w h t i w n e k a t e r a s r e b m u n g n i m i t l l a , e s i w r e h t o d e t o n s s e l n u . 4 . y a r r a d n a d e e p s . r e v i r d t u p t u o e v i t c a l a m r o n g n i s u d e r u s a e m s r e t e m a r a p g n i m i t . 5 s i o i c c v n e h w d e r r u c n i s i y a l e d s n 5 . 0 l a n o i t i d d a n a . e c n e r e f e r e g a t l o v o / i s a c c v h t i w d e r u s a e m e r a s r e t e m a r a p y a l e d e h t . 6 . e c n e r e f e r e g a t l o v o / i s a d e s u . r o i v a h e b t u p t u o n w o n k n u e s u a c y a m m u m i n i m n a h t s s e l s h t d i w e s l u p . 7
specifications isplsi 5128ve 14 external switching characteristics over recommended operating conditions . m a r a p t s e t 3 . d n o c n o i t p i r c s e d 5 , 4 0 0 1 -0 8 - s t i n u . n i m. x a m. n i m. x a m t 1 d p 6 as s a p y b t p 5 , y a l e d . p o r p a t a d?0 . 0 1? 0 . 2 1s n t 2 d p 6 ay a l e d n o i t a g a p o r p a t a d?0 . 2 1? 0 . 5 1s n f x a m ak c a b d e e f l a n r e t n i h t i w y c n e u q e r f k c o l c 1 0 0 1?0 8? z h m f ) . t x e ( x a m ?) 1 o c t + 2 u s t ( / 1 , k c a b d e e f . t x e h t i w . q e r f k c o l c7 6?6 5? z h m f ) . g o t ( x a m ?e l g g o t x a m , y c n e u q e r f k c o l c 2 5 2 1? 0 0 1? z h m t 1 u s ?s s a p y b t p 5 , k l c e r o f e b e m i t p u t e s . g e r b l g0 . 7?0 . 8? s n t 1 o c 6 ay a l e d t u p t u o o t k c o l c . g e r b l g?0 . 6?0 . 7s n t 1 h ?s s a p y b t p 5 , k c o l c r e t f a e m i t d l o h . g e r b l g0 . 0?0 . 0? s n t 2 u s ?k c o l c e r o f e b e m i t p u t e s . g e r b l g0 . 9? 0 . 1 1?s n t 2 h ?k c o l c r e t f a e m i t d l o h . g e r b l g0 . 0?0 . 0? s n t 3 u s ?h t a p . g e r t u p n i , k c o l c e r o f e b e m i t p u t e s . g e r b l g5 . 4?5 . 5? s n t 3 h ?h t a p . g e r t u p n i , k c o l c r e t f a e m i t d l o h . g e r b l g 0 . 1? 0 . 1? s n t 1 r ay a l e d t u p t u o o t n i p t e s e r . t x e?5 . 1 1? 0 . 3 1s n t 1 w r 7 ?n o i t a r u d e s l u p t e s e r . t x e 5 . 6?0 . 8? s n t s i d / n e t p 6 c / be l b a s i d / e l b a n e t u p t u o m r e t t c u d o r p l a c o l?0 . 0 1? 0 . 2 1s n t s i d / n e t p g 6 c / be l b a s i d / e l b a n e t u p t u o m r e t t c u d o r p l a b o l g?5 . 5 1? 0 . 7 1s n t s i d / n e g 6 c / be l b a s i d / e l b a n e t u p t u o o t t u p n i e o l a b o l g?5 . 7?0 . 9s n t s i d / n e t 6 c / be l b a s i d / e l b a n e t u p t u o o t t u p n i e o t s e t?5 . 1 1? 5 . 2 1s n t h w ?h g i h , n o i t a r u d e s l u p k c o l c . c n y s . t x e 0 . 4?0 . 5? s n t l w ?w o l , n o i t a r u d e s l u p k c o l c . c n y s . t x e 0 . 4?0 . 5? s n . k c a b d e e f p r g g n i s u r e t n u o c t i b - 6 1 d r a d n a t s . 1 s p e . 2 e v 8 2 1 5 . t x e g n i m i t . % 0 5 n a h t r e h t o f o e l c y c y t u d k c o l c a r o f w o l l a o t s i s i h t . ) l w t + h w t ( / 1 n a h t s s e l e b y a m ) e l g g o t ( x a m f . 2 0 . 2 . v g n i m i t . n o i t c e s s n o i t i d n o c t s e t g n i h c t i w s e c n e r e f e r . 3 - h g i h d n a , 0 k l c , b l g 1 f o d a o l p r g a , t u o n a f a s t p e s a c t s r o w h t i w n e k a t e r a s r e b m u n g n i m i t l l a , e s i w r e h t o d e t o n s s e l n u . 4 . y a r r a d n a d e e p s . r e v i r d t u p t u o e v i t c a l a m r o n g n i s u d e r u s a e m s r e t e m a r a p g n i m i t . 5 s i o i c c v n e h w d e r r u c n i s i y a l e d s n 5 . 0 l a n o i t i d d a n a . e c n e r e f e r e g a t l o v o / i s a c c v h t i w d e r u s a e m e r a s r e t e m a r a p y a l e d e h t . 6 . e c n e r e f e r o / i s a d e s u . r o i v a h e b t u p t u o n w o n k n u e s u a c y a m m u m i n i m n a h t s s e l s h t d i w e s l u p . 7 . e c n e r e f e r e g a t l o v o / i s a d e s u
specifications isplsi 5128ve 15 internal timing parameters over recommended operating conditions in/out delays t in input buffer delay ? 0.9 ? 1.3 ? 2.3 ? 2.3 ns t gclk_in global clock buffer input delay (clk0) ? 1.0 ? 1.3 ? 1.8 ? 1.8 ns t rst global reset pin delay ? 4.4 ? 6.6 ? 7.1 ? 7.1 ns t goe global oe pin delay ? 2.5 ? 3.9 ? 5.9 ? 7.4 ns t buf output buffer delay ? 1.1 ? 2.2 ? 2.7 ? 3.7 ns t en output enable delay ? 1.0 ? 1.6 ? 1.6 ? 1.6 ns t dis output disable delay ? 1.0 ? 1.6 ? 1.6 ? 1.6 ns routing/glb delays t route grp and logic delay ? 2.7 ? 3.6 ? 4.0 ? 4.5 ns t pdb 5-pt bypass propagation delay ? 0.3 ? 0.4 ? 1.0 ? 1.5 ns t pdi combinatorial propagation delay ? 1.0 ? 0.0 ? 0.0 ? 0.0 ns t ptsa product term sharing array ? 1.3 ? 2.4 ? 3.0 ? 4.5 ns t fbk internal feedback delay ? 0.0 ? 0.0 ? 0.0 ? 0.5 ns t inreg input buffer to macrocell register delay ? 2.0 ? 2.5 ? 2.5 ? 3.5 ns register/latch delays t s register setup time 0.6 ? 1.0 ? 1.5 ? 1.5 ? ns t s_pt register setup time (product term clock) 0.6 ? 1.0 ? 1.5 ? 1.5 ? ns t h register hold time 2.4 ? 3.0 ? 4.0 ? 5.0 ? ns t coi register clock to glb output delay ? 0.9 ? 1.0 ? 1.5 ? 1.5 ns t sl latch setup time 0.6 ? 1.0 ? 1.5 ? 1.5 ? ns t hl latch hold time 2.4 ? 3.0 ? 4.0 ? 5.0 ? ns t goi latch gate to glb output delay ? 0.9 ? 1.0 ? 1.5 ? 1.5 ns t pdli glb latch propagation delay ? 1.0 ? 1.5 ? 2.0 ? 2.5 ns t ces clock enable setup time 4.1 ? 4.3 ? 5.3 ? 6.3 ? ns t ceh clock enable hold time 0.3 ? 1.7 ? 2.7 ? 3.7 ? ns t sri asynchronous set/reset to glb output delay ? 0.5 ? 1.2 ? 1.7 ? 2.2 ns t srr asynchronous set/reset recovery time 1.1 ? 1.2 ? 1.2 ? 2.2 ? ns control delays t ptclk macrocell pt clock delay ? 0.4 ? 0.4 ? 0.5 ? 0.5 ns t bclk block pt clock delay ? 1.4 ? 1.9 ? 2.5 ? 2.5 ns t ptsr macrocell pt set/reset delay ? 1.8 ? 3.7 ? 4.8 ? 4.8 ns t bsr block pt set/reset delay ? 2.8 ? 5.7 ? 6.8 ? 6.8 ns t ptoe macrocell pt oe delay ? 1.4 ? 2.0 ? 2.1 ? 3.6 ns t gptoe global pt oe delay ? 2.4 ? 7.5 ? 7.6 ? 8.6 ns -180 -125 -100 -80 min max min max min max min max unit parameter description note: internal timing parameters are not tested and are for reference only. refer to timing model in this data sheet for further details. timing v.2.0
specifications isplsi 5128ve 16 isplsi 5128ve timing parameters (continued) tioi input adders routing adders tioo output adders 1 tbla additional block loading adders units adder -100 -80 base parameter adder type clk1 clk3 1.7 ns clk2 1.7 ns slow slew i/o ns 1 0.1 ns 2 0.2 ns 3 0.3 ns lvcmos25_out 0.5 ns ns t gclk_in t gclk_in t gclk_in t route t route t route t buf, t en, t dis t buf, t en 1.7 1.7 1.7 1.7 4.0 4.0 0.1 0.2 0.3 0.5 -125 -180 1.7 1.7 0.1 0.2 0.3 0.5 0.9 t lp 1.5 ns t route 1.5 1.5 1.0 1.4 1.7 1.4 4.0 4.0 0.1 0.2 0.3 0.5 lvcmos33_out 0.0 ns t buf, t en, t dis 0.0 0.0 0.0 lvttl_out 0.0 ns t buf, t en, t dis 0.0 0.0 0.0 timing table/5128ve timing v.2.0 1 timing for open drain configurations is the same as non-open drain configurations. note: internal timing parameters are not tested and are for reference only. refer to timing model in this data sheet for details.
specifications isplsi 5128ve 17 t bla t lp t ioi t bsr t ptsr t gptoe t ptoe t pdi t goe t rst t in t inreg t route t pdb t fbk t buf t ioo t en t dis t ptsa t ptclk t bclk t gclk_in in q oe from feedback in/ou t delays in/ou t delays rou t ing/ glb delays regis t er/ la t ch delays con t rol delays feedbac k out data mc reg ce s/r clk rst no t e: i t alicized parame t ers are delay adders above and beyond defaul t condi t ions (i.e. grp load of one glb, clk0, high-speed and array and vcc i/o op t ion). 5000ve timing model isplsi 5128ve timing model
specifications isplsi 5128ve 18 power consumption setting operates product terms at their normal full power consumption. for portions of the logic that can tolerate longer propagation delays, selecting the slower ?low- power? setting will reduce the power dissipation for these product terms. figure 10 shows the relationship between power and operating frequency. power consumption in the isplsi 5128ve device de- pends on two primary factors: the speed at which the device is operating and the number of product terms used. the product terms have a fuse-selectable speed/ power tradeoff setting. each group of five product terms has a single speed/power tradeoff control fuse that acts on the complete group of five. the fast ?high-speed? 105 0255075 100 125 150 175 200 f max (mhz) i cc (ma) notes: configuration of 8 16-bit counters typical current at 3.3v, 25 c isplsi 5128ve high speed mode isplsi 5128ve low power mode 0127/5128ve i cc can be estimated for the isplsi 5128ve using the following equation: high speed mode: icc = 12.4 + (# of pts * 0.408) + (# of nets * fmax * 0.00169) low power mode: icc = 12.4 + (# of pts * 0.349) + (# of nets * fmax * 0.00169) # of pts = number of product terms used in design # of nets = number of signals used in device fmax = highest clock frequency to the device the i cc estimate is based on typical conditions (v cc = 3.3v, room temperature) and an assumption of one glb load on average exists. these values are for estimates only. since the value of i cc is sensitive to operating conditions and the program in the device, the actual i cc should be verified. 135 165 180 150 120 90 figure 10. typical device power consumption vs fmax
specifications isplsi 5128ve 19 tms input - this pin is the test mode select input, which is used to control the jtag state machine. tck input - this pin is the test clock input pin used to clock through the jtag state machine. tdi input - this pin is the jtag test data in pin used to load data. tdo output - this pin is the jtag test data out pin used to shift data out. toe / i/o0 input/output - this pin functions as either the test output enable pin or an i/o pin based upon customer's design. toe tristates all i/o pins when a logic low is driven. goe0, goe1 input - these two pins are the global output enable input pins. reset dedicated reset input - this pin resets all registers in the device. the global polarity (active high or low input) for this pin is selectable. i/o input/output ? these are the general purpose i/o used by the logic array. gnd ground vcc vcc clk0, clk1 dedicated clock inputs for all registers. both clocks are muxed before being used as the clock input to all registers in the device. clk2 / i/o, input/output - these pins share functionality. they can be used as dedicated clock inputs for clk3 / i/o all registers, as well as i/o pins. vccio input - this pin is used for optional 2.5v outputs. every i/o can independently select either 3.3v or the optional voltage as its output level. if the optional output voltage is not required, this pin must be connected to the vcc supply. programmable pull-up resistors and bus-hold latches only draw current from this supply. signal descriptions signal name description
specifications isplsi 5128ve 20 pin configuration isplsi 5128ve 128-pin tqfp (0.4mm lead pitch / 14.0mm x 14.0mm body size) i/o 83 i/o 82 i/o 84 i/o 85 i/o 86 i/o 87 gnd i/o 88 vcc i/o 89 i/o 90 i/o 91 i/o 92 i/o 93 i/o 94 i/o 95 gnd tms tck vcc i/o 0/toe i/o 1 i/o 2 i/o 3 i/o 4 gnd i/o 5 vcc i/o 6 i/o 56 i/o 55 i/o 54 i/o 53 i/o 52 i/o 51 i/o 50 i/o 49 i/o 48 vcc reset vccio tdo gnd i/o 47 i/o 46 i/o 44 i/o 43 i/o 42 vcc i/o 41 gnd i/o 40 i/o 39 i/o 38 i/o 37 i/o 36 gnd i/o 35 i/o 81 i/o 80 i/o 79 vcc i/o 78 gnd i/o 77 i/o 76 i/o 75 i/o 74 i/o 73 i/o 72 i/o 71 vcc clk0 i/o 69 gnd i/o 68 i/o 67 i/o 66 i/o 65/clk3 i/o 64 i/o 63 i/o 62 i/o 61 i/o 60 gnd i/o 59/clk2 i/o 58 i/o 57 i/o 8 i/o 10 i/o 11 i/o 12 gnd i/o 13 i/o 14 vcc i/o 15 i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 22 i/o 23 gnd goe0 goe1 vcc i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 i/o 32 i/o 33 isplsi 5128ve top view i/o 7 tdi vcc i/o 70 i/o 45 vcc i/o 9 i/o 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 128 127 126 125 124 123 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 64 96 122 i/o 34 clk1 128 tqfp/5128ve
specifications isplsi 5128ve 21 part number description ordering information device number grade blank = commercial i = industrial isplsi 5128ve xxx x xxxx speed 180 = 180 mhz f max 125 = 125 mhz f max 100 = 100 mhz f max 80 = 80 mhz f max power l = low package t128 = 128-pin tqfp ? device family x 0212/5128ve table 2-0041a/5128ve family f max (mhz) ordering number package t pd (ns) isplsi 180 128-pin tqfp 5.0 isplsi 5128ve-180lt128 125 128-pin tqfp 7.5 isplsi 5128ve-125lt128 100 128-pin tqfp 10 isplsi 5128ve-100lt128 commercial table 2-0041b/5128ve family f max (mhz) ordering number package t pd (ns) isplsi 125 128-pin tqfp 7.5 isplsi 5128ve-125lt128i 100 128-pin tqfp 10 isplsi 5128ve-100lt128i 80 128-pin tqfp 12 isplsi 5128ve-80lt128i industrial the isplsi 5128ve is dual-marked with both commercial and industrial grades. the commercial speed grade is faster (i.e. isplsi 5128ve-180lt128) than the industrial speed grade (i.e. isplsi 5128ve-125lt128i).

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